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preliminary clock synthesizer with differential cpu outputs cy28346-2 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07509 rev. *b revised march 11, 2005 features ? compliant with intel ? ck 408 mobile clock synthesizer specifications ? 3.3v power supply ? 3 differential cpu clocks ? 10 copies of pci clocks ? 5/6 copies of 3v66 clocks ? smbus support with re ad back capabilities ? spread spectrum electromagnetic interference (emi) reduction ? dial-a-frequency ? features ? dial-a-db? features ? extended operating temperature range, 0 c to 85 c ? 56-pin tssop packages note: 1. tclk is a test clock driven on the xtal_in input during test mode. m = driven to a level between 1.0v and 1.8v. if the s2 pin is at a m level during power-up, a 0 state will be latched into the devices internal state register. table 1. frequency table [1] s2 s1 s0 cpu (0:2) 3v66 66buff(0:2)/ 3v66(0:4) 66in/ 3v66-5 pcif/pci ref usb/ dot 1 0 0 66m 66m 66in 66-mhz clock input 66in/2 14.318m 48m 1 0 1 100m 66m 66in 66-mhz clock input 66in/2 14.318m 48m 1 1 0 200m 66m 66in 66-mhz clock input 66in/2 14.318m 48m 1 1 1 133m 66m 66in 66-mhz clock input 66in/2 14.318m 48m 0 0 0 66m 66m 66m 66m 33 m 14.318m 48m 0 0 1 100m 66m 66m 66m 33 m 14.318m 48m 0 1 0 200m 66m 66m 66m 33 m 14.318m 48m 0 1 1 133m 66m 66m 66m 33 m 14.318m 48m m 0 0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z m 0 1 tclk/2 tclk/4 tclk/4 tclk/4 tclk/8 tclk tclk/2 pll1 pll2 /2 wd logic power up logic xin xout cpu_stp# iref vssiref s(0:2) mult0 vtt_pwrgd# pci_stp# pd# sdata sclk vdda 66b[0:2]/3v66[2:4] 48m_dot 48m_usb pci_f(0:2) pci(0:6) 3v66_1/vch 3v66_0 cpuc(0:2) cput(0:2) ref 66in/3v66-5 i2c logic vdd xin xout vss pcif0 pcif1 pcif2 vdd vss pci0 pci1 pci2 pci3 vdd vss pci4 pci5 pci6 vdd vss 66b0/3v66_2 66b1/3v66_3 66b2/3v66_4 66in/3v66_5 pd# vdda vssa vtt_pwrgd# ref s1 s0 cpu_stp# cput0 cpuc0 vdd cput1 cpuc1 vss vdd cput2 cpuc2 mult0 iref vssiref s2 48m_usb 48m_dot vdd vss 3v66_1/vch pci_stp# 3v66_0 vdd vss sclk sdata 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 cy28346-2 block diagram pin configuration
preliminary cy28346-2 document #: 38-07509 rev. *b page 2 of 20 pin description pin name pwr i/o description 2xin vddi oscillator buffer input . connect to a crystal or to an external clock. 3xout vddo oscillator buffer output . connect to a crystal. do not connect when an external clock is applied at xin. 52, 51, 49, 48, 45, 44 cput(0:2), cpuc(0:2) vdd o differential host output clock pairs . see table 1 for frequencies and functionality. 10, 11, 12, 13, 16, 17, 18 pci(0:6) vddp o pci clock outputs . are synchronous to 66in or 3v66 clock. see ta ble 1 . 5, 6, 7 pcif (0:2) vdd o 33-mhz pci clocks, which are 2 copies of 66in or 3v66 clocks, may be free running (not stopped when pci_stp# is asserted low) or may be stoppable depending on the programming of smbus register byte3, bits (3:5) . 56 ref vdd o buffered output copy of the device?s xin clock . 42 iref vdd i current reference programmi ng input for cpu buffers . a resistor is connected between th is pin and vssiref. 28 vtt_pwrgd# vdd i qualifying input that latches s(0:2) and mult0 . when this input is at a logic low, the s(0:2) and mult0 are latched. 39 48m_usb vdd48 o fixed 48-mhz usb clock outputs . 38 48m_dot vdd48 o fixed 48-mhz dot clock outputs . 33 3v66_0 vdd o 3.3v 66-mhz fixed frequency clock . 35 3v66_1/vch vdd o 3.3v clock selectable with smbus byte0, bit5, when byte5, bit5 . when byte 0 bit 5 is at a logic 1, then this pin is a 48m output clock. when byte0, bit5 is a logic 0, then th is is a 66m output clock (default). 25 pd# vdd i pu this pin is a power-down mode pin . a logic low level causes the device to enter a power-down state. all internal logic is turned off except for the smbus logic. all output buffers are stopped. 43 mult0 vdd i pu programming input selection fo r cpu clock current multiplier . 55, 54 s(0,1) i i frequency select inputs . see table 1 29 sdata i i serial data input . conforms to the smbus specification of a slave receive/transmit device. it is an input when receiving data. it is an open drain output when acknowledging or transmitting data. 30 sclk i i serial clock input . conforms to the smbus specification. 40 s2 vdd i t frequency select input . see table 1 . this is a tri-level input that is driven high, low, or driven to a intermediate level. 34 pci_stp# vdd i pu pci clock disable input . when asserted low, pci (0:6) clocks are synchronously disabled in a low state. this pin does not effect pcif (0:2) clocks? outputs if they are pr ogrammed to be pcif clocks via the device?s smbus interface. 53 cpu_stp# vdd i pu cpu clock disable input . when asserted low, cput (0:2) clocks are synchronously disabled in a high state and cpuc(0:2) clocks are synchronously disabled in a low state. 24 66in/3v66_5 vdd i/o input connection for 66clk(0:2) ou tput clock buffers if s2 = 1 , or output clock for fixed 66-mhz clock if s2 = 0. see table 1 . 21, 22, 23 66b(0:2)/ 3v66(2:4) vdd o 3.3v clock outputs . these clocks are buffered copies of the 66in clock or fixed at 66 mhz. see ta ble 1 . 1, 8, 14, 19, 32, 37, 46, 50 vdd ? pwr 3.3v power supply . 4, 9, 15, 20, 27, 31, 36, 47 vss ? pwr common ground .
preliminary cy28346-2 document #: 38-07509 rev. *b page 3 of 20 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts block write and block read operations from the cont roller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. the block write and block read protocol is outlined in table 2 . the slave receiver address is 11010010 (d2h). 41 vssiref ? pwr current reference programmi ng input for cpu buffers . a resistor is connected between this pin and iref. this pin should also be returned to device vss. 26 vdda ? pwr analog power input . used for pll and internal analog circuits. it is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. pin description (continued) pin name pwr i/o description table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bit ?00000000? stands for block operation 11:18 command code ? 8 bit ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 2 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... ...................... 39:46 data byte from slave ? 8 bits .... data byte (n?1) ?8 bits 47 acknowledge .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... data byte n ?8 bits 56 acknowledge .... acknowledge from slave .... data bytes from slave/acknowledge .... stop .... data byte n from slave ? 8 bits .... not acknowledge .... stop
preliminary cy28346-2 document #: 38-07509 rev. *b page 4 of 20 byte 0 : cpu clock register bit @pup name description 7 0 spread spectrum enable, 0 = spread off, 1 = spread on. this is a read and write control bit. 60 cpu clock power-down mode select. 0 = drive cput(0:2) to 4 or 6 iref and drive cpuc(0:2) to low when pd# is asserted low. 1 = three-state all cpu outputs. this is only applicable when pd# is low. it is not applicable to cpu_stp#. 50 3v66_1/vch 3v66_1/vch frequency select , 0 = 66m selected, 1 = 48m selected this is a read and write control bit. 4 pin 53 cput,cpuc cpu_stp#. reflects the current value of the external cpu_stp# (pin 53) this bit is read-only. 3pin 34 pci reflects the current value of the internal pci_ stp# function when read. internally pci_stp# is a logical and function of the internal smbus register bit and the external pci_stp# pin. 2 pin 40 frequency select bit 2. reflects the value of sel2 (pin 40). this bit is read-only. 1 pin 55 frequency select bit 1. reflects the value of sel1 (pin 55). this bit is read-only. 0 pin 54 frequency select bit 0. reflects the value of sel0 (pin 54). this bit is read-only. byte 1 : cpu clock register bit @pup name description 7 pin 43 mult0 mult0 (pin 43) value. this bit is read-only. 6 0 cpu_stp# controls functionality of cput/c(0:2) outputs when cpu_stp# is asserted. 0 = drive cput(0:2) to 4 or 6 iref and drive cpuc(0:2) to low when cpu_stp# asserted low. 1 = three-state all cpu outputs. this bit will override byte0, bit6 such that even if it is a 0, when pd# goes low the cpu outputs will be three-stated. 50 cput2 cpuc2 controls cpu2 functionality when cpu_stp# is asserted low 1 = free running, 0 = stopped low with cpu_stp# asserted low this is a read and write control bit. 40 cput1 cpuc1 controls cpu1 functionality when cpu_stp# is asserted low 1 = free running, 0 = stopped low with cpu_stp# asserted low this is a read and write control bit. 30 cput0 cpuc0 controls cput0 functionality when cpu_stp# is asserted low 1 = free running, 0 = stopped low with cpu_stp# asserted low this is a read and write control bit. 21 cput2 cpuc2 cput/c2 output control, 1 = enabled, 0 = disable high and cpuc2 disables low this is a read and write control bit. 11 cput1 cpuc1 cput/c1 output control, 1 = enabled, 0 = disable high and cpuc1 disables low this is a read and write control bit. 01 cput0 cpuc0 cput/c0 output control, 1 = enabled, 0 = disable high and cpuc0 disables low this is a read and write control bit. byte 2 : pci clock control register (all bits are read and write functional) bit @pup name description 7 0 ref ref output control. 0 = high strength, 1 = low strength 6 1 pci6 pci6 output control. 1 = enabled, 0 = forced low 5 1 pci5 pci5 output control. 1 = enabled, 0 = forced low 4 1 pci4 pci4 output control. 1 = enabled, 0 = forced low 3 1 pci3 pci3 output control. 1 = enabled, 0 = forced low 2 1 pci2 pci2 output control. 1 = enabled, 0 = forced low 1 1 pci1 pci1 output control. 1 = enabled, 0 = forced low 0 1 pci0 pci0 output control. 1 = enabled, 0 = forced low
preliminary cy28346-2 document #: 38-07509 rev. *b page 5 of 20 byte 3 : pcif clock and 48m control register (all bits are read and write functional) bit @pup name description 7 1 48m_dot 48m_dot output control,1 = enabled, 0 = forced low 6 1 48m_usb 48m_usb output contro l,1 = enabled, 0 = forced low 5 0 pcif2 pci_stp#, control of pcif2. 0 = free running, 1 = stopped when pci_stp# is low 4 0 pcif1 pci_stp#, control of pcif1. 0 = free running, 1 = stopped when pci_stp# is low 3 0 pcif0 pci_stp#, control of pcif0. 0 = free running, 1 = stopped when pci_stp# is low 2 1 pcif2 pcif2 output contro l. 1=running, 0=forced low 1 1 pcif1 pcif1 output control. 1= running, 0=forced low 0 1 pcif0 pcif0 output control. 1= running, 0=forced low byte 4 : drcg control register (all bits are read and write functional) bit @pup name description 7 0 ss2 spread spectrum control bit (0 = down spread, 1 = center spread) 60 reserved 5 1 3v66_0 3v66_0 output enabled. 1 = enabled, 0 = disabled 4 1 3v66_1/vch 3v66_1/vch output en able. 1 = enabled, 0 = disabled 3 1 3v66_5 3v66_5 output enable. 1 = enabled, 0 = disabled 2 1 66b2/3v66_4 66b2/3v66_4 output enabled. 1 = enabled, 0 = disabled 1 1 66b1/3v66_3 66b1/3v66_3 output enabled. 1 = enabled, 0 = disabled 0 1 66b0/3v66_2 66b0/3v66_2 output enabled. 1 = enabled, 0 = disabled byte 5 : clock control register (all bits are read and write functional) bit @pup name description 7 0 ss1 spread spectrum control bit 6 1 ss0 spread spectrum control bit 5 0 66in to 66m delay control msb 4 0 66in to 66m delay control lsb 30 reserved 2 0 48m_dot edge rate control. when set to 1, the edge is slowed by 15%. 10 reserved 0 0 usb edge rate control. when set to 1, the edge is slowed by 15% byte 6 : silicon signature register [2] (all bits are read-only) bit @pup name description 70 60 50 41 3 0 vendor code, 011 = imi 20 11 01 note: 2. when writing to this register the device will acknowledge the write operation, but the data itself will be ignored.
preliminary cy28346-2 document #: 38-07509 rev. *b page 6 of 20 dial-a-frequency feature smbus dial-a-frequency feature is available in this device via byte8 and byte9. see our app no te an-0025 for details on our dial-a-frequency feature. p is a large value pll consta nt that depends on the frequency selection achieved through th e hardware selectors (s1, s0). p value may be determined from table 3 . dial-a-db features smbus dial-a-db feature is avai lable in this device via byte8 and byte9. spread spectrum clock generation (sscg) spread spectrum is a modulation technique used to minimizing emi radiation gen erated by repetitive digital signals. a clock presents the greatest emi energy at the center frequency it is generating. spread spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. this technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of emi reduction). in this device, spread spectrum is enabled by setting specific register bits in the smbus control bytes. table 4 is a listing of the modes and percentages of spread spectrum modulation that this device incorporates. byte 7 : watchdog time stamp register bit @pup name description 70 reserved 60 reserved 50 reserved 40 reserved 30 reserved 20 reserved 10 reserved 00 reserved byte 8 : dial-a-frequency control register n (all bits are read and write functional) bit @pup name description 70 n7, msb 60 n6 50 n5 40 n4 30 n3 20 n2 10 n3 00 n0, lsb byte 9 : dial-a-frequency control register r (all bits are read and write functional) bit @pup name description 70 r6 msb 60 r5 50 r4 40 r3 30 r2 20 r1 10 r0, lsb 0 0 r and n register load gate 0 = gate closed (data is latched), 1 = gate open (data is loading from smbus registers into r and n) table 3. p value s(1:0) p 0 0 32005333 0 1 48008000 1 0 96016000 1 1 64010667
preliminary cy28346-2 document #: 38-07509 rev. *b page 7 of 20 special functions pcif and ioapic clock outputs the pcif clock outputs are intended to be used, if required, for systems ioapic clock function ality. any two of the pcif clock outputs can be used as ioapic 33-mhz clock outputs. they are 3.3v outputs will be divided down via a simple resistive voltage divider to me et specific system ioapic clock voltage requirements. in the event these clocks are not required, then these clocks can be used as general pci clocks or disabled via the assertion of the pci_stp# pin. 3v66_1/vch clock output the 3v66_1/vch pin has a dual functionality that is selectable via smbus. configured as drcg (66m), smbus byte0, bit 5 = ?0? the default condition for this pin is to power up in a 66m operation. in 66m operation th is output is sscg capable and when spreading is turned on, this clock will be modulated. configured as vch (48m), smbus byte0, bit 5 = ?1? in this mode, the output is configured as a 48-mhz non-spread spectrum output. this output is phase aligned with the other 48m outputs (usb and dot), to within 1 ns pin-to-pin skew. the switching of 3v66_1/vch into vch mode occurs at system power on. when the smbus bit 5 of byte 0 is programmed from a ?0? to a ?1 ?, the 3v66_1/ vch output may glitch while transitioning to 48m output mode. pd# (power-down) clarification the pd# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. pd# is an asynchronous active low input. this signal is synchronized internally to the device powering down the cl ock synthesizer. pd# is an asynchronous function for powering up the system. when pd# is low, all clocks are driven to a low value and held there and the vco and plls are also powered down. all clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ?stopped? state. pd#?assertion when pd# is sampled low by two consecutive rising edges of the cpuc clock, then on the next high-to-low transition of pcif, the pcif clock is stopped low. on the next high-to-low transition of 66buff, the 66buff clock is stopped low. from this time, each clock will stop low on its next high-to-low transition, except the cput clock. the cpu clocks are held with the cput clock pin driven high with a value of 2 x iref, and cpuc undriven. after the last clock has stopped, the rest of the generator will be shut down. table 4. spread spectrum ss2 ss1 ss0 spread mode spread% 0 0 0 down +0.00, ?0.25 0 0 1 down +0.00, ?0.50 0 1 0 down +0.00, ?0.75 0 1 1 down +0.00, ?1.00 1 0 0 center +0.13, ?0.13 1 0 1 center +0.25, ?0.25 1 1 0 center +0.37, ?0.37 1 1 1 center +0.50, ?1.50 66buff pcif pwrdwn# cpu 133mhz cpu# 133mhz 3v66 66in ref 14.318mhz usb 48mhz figure 1. power-down assertion timing waveforms?buffered mode
preliminary cy28346-2 document #: 38-07509 rev. *b page 8 of 20 pd# deassertion the power-up latency between pd# rising to a valid logic ?1? level and the starting of all clocks is less than 3.0 ms. pci 33mhz pwrdwn# cput 133mhz cpuc 133mhz ref 14.318mhz usb 48mhz sdram 133mhz ddrt 133mhz ddrc 133mhz agp 66mhz figure 2. power-down assertion timing waveforms?unbuffered mode cpu 133mhz 3v66 cpu# 133mhz ref 14.318mhz usb 48mhz pcif / apic 33mhz 66in 66buff pwrdwn# 66buff1 / gmch 400us max <1.8ms pci 33mhz 30us min figure 3. power-down deassertion timing waveforms table 5. pd# functionality pd# drcg 66clk (0:2) pcif/pci pci usb/dot 1 66m 66input 66inpu t/2 66input/2 48m 0 low low low low low
preliminary cy28346-2 document #: 38-07509 rev. *b page 9 of 20 cpu_stp# clarification the cpu_stp# signal is an active low input used for synchronous stopping and starting the cpu output clocks while the rest of the clock gen erator continues to function. cpu_stp# assertion when cpu_stp# pin is asserted, all cput/c outputs that are set with the smbus configuration to be stoppable via assertion of cpu_stp# will be stopped after being sampled by two falling cput/c clock edges. the final state of the stopped cpu signals is cput = high and cpu0c = low. there is no change to the output drive cu rrent values during the stopped state. the cput is driven high with a current value equal to (mult 0 ?select?) x (iref), and the cpuc signal will not be driven. due to external pull-down circuitry cpuc will be low during this stopped state. cpu_stp# deassertion the deassertion of the cpu_stp# signal will cause all cput/c outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. the maximum latency from the deassertion to active outputs is no more than two cpuc clock cycles. cpu_stp# cput cpuc cput cpuc figure 4. cpu_stp# assertion waveforms cpu_stp# cput cpuc cput cpuc figure 5. cpu_stp# deassertion waveforms
preliminary cy28346-2 document #: 38-07509 rev. *b page 10 of 20 three-state control of cpu clocks clarification during cpu_stp# and pd# modes, cpu clock outputs may be set to driven or undriven (t hree-state) by setting the corre- sponding smbus entry in bit6 of byte0 and bit6 of byte1. pci_stp# assertion the pci_stp# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator co ntinues to function. the set-up time for capturing pci_stp# going low is 10 ns (t setup ). (see figure 2 .) the pcif (0:2) clocks will not be affected by this pin if their control bits in the smbus register are set to allow them to be free running. pci_stp# deassertion the deassertion of the pci_stp# signal will cause all pci and stoppable pcif clocks to resume running in a synchronous manner within two pci clock periods after pci_stp# transi- tions to a high level. note that the pci stop function is controlled by two inputs. one is the device pci_stp# pin number 34 and the other is smbus byte 0 bit 3. these two inputs to the function are logically anded. if either t he external pin or the internal smbus register bit is set low then the stoppable pci clocks will be stopped in a logic low state. reading smbus byte 0 bit 3 will return a 0 value if either of these control bits are set low thereby indicating the device s stoppable pci clocks are not running. table 6. cypress clock power management truth table b0b6 b1b6 pd# cpu_stp# stoppable cput stoppable cpuc non-stop cput non-stop cpuc 0 0 1 1 running running running running 0 0 1 0 iref x6 iref x6 running running 0 0 0 1 iref x2 low iref x2 low 0 0 0 0 iref x2 low iref x2 low 0 1 1 1 running running running running 0 1 1 0 hi z hi z running running 0 1 0 1 hi z hi z hi z hi z 0 1 0 0 hi z hi z hi z hi z 1 0 1 1 running running running running 1 0 1 0 iref x6 iref x6 running running 1 0 0 1 hi z hi z hi z hi z 1 0 0 0 hi z hi z hi z hi z 1 1 1 1 running running running running 1 1 1 0 hi z hi z running running 1 1 0 1 hi z hi z hi z hi z 1 1 0 0 hi z hi z hi z hi z pci_stp# pcif 33m pci 33m setup t figure 6. pci_stp# assertion waveforms
preliminary cy28346-2 document #: 38-07509 rev. *b page 11 of 20 iout is selectable depending on implementation. the param- eters above apply to all configurations. vout is the voltage at the pin of the device. the various output current conf igurations are shown in the host swing select functions tabl e. for all configurations, the deviation from the expected output current is 7% as shown in the current accuracy table. pci_stp# pcif pci setup t figure 7. pci_stp# deassertion waveforms figure 8. vtt_pwrgd# timing diagram vid sel vtt_pwrgd# pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored. vtt_pwrgd# = low delay >0.25ms s1 power off s0 vdda = 2.0v sample inputs straps s2 normal operation wait for <1.8ms enable outputs s3 vtt_pwrgd# = toggle vdd3.3= off figure 9. clock generator power-up/run state program
preliminary cy28346-2 document #: 38-07509 rev. *b page 12 of 20 usb and dot 48m phase relationship the 48m_usb and 48m_dot clocks are in phase. it is under- stood that the difference in edge rate will introduce some in inherent offset. when 3v66_1/vch clock is configured for vch (48-mhz) operation it is also in phase with the usb and dot outputs. see figure 10 . 66in to 66b buffered prop delay the 66in to 66b(0:2) output delay is shown in figure 11 . the tpd is the prop delay from the input pin (66in) to the output pins (66b[0:2]). the outputs? variation of tpd is described in the ac parameters se ction of this data sheet. the measurement is taken at 1.5v. 66b to pci buffered clock skew figure 12 shows the difference (skew) between the 3v33(0:5) outputs when the 66m clocks are connected to 66in. this offset is described in the group timing relationship and toler- ances section of this data sheet. the measurements were taken at 1.5v. 3v66 to pci unbuffered clock skew figure 13 shows the timing relationship between 3v66(0:5) and pci(0:6) and pcif when configured to run in the unbuf- fered mode. table 7. host clock (hcsl) buffer characteristics characteristic minimum maximum ro 3000 ohms (recommended) n/a ros vout n/a 1.2v table 8. cpu clock current select function mult0 board target trace/term z reference r, iref ? vdd (3*rr) output current voh @ z 0 50 ohms rr = 221 1%, iref = 5.00 ma ioh = 4*iref 1.0v @ 50 1 50 ohms rr = 475 1%, iref = 2.32 ma ioh = 6*iref 0.7v @ 50 table 9. group timing relationship and tolerances description offset tolerance conditions 3v66 to pci 2.5 ns 1.0 ns 3v66 leads pci (unbuffered mode) 48m_usb to 48m_dot skew 0.0 ns 1.0 ns 0 degrees phase shift 66b to pci offset 2.5 ns 1.0 ns 66b leads pci (buffered mode) table 10.maximum lumped capacitive output loads clock max load unit pci clocks 30 pf 3v66 30 pf 66b 30 pf 48m_usb clock 20 pf 48m_dot 10 pf ref clock 50 pf 48musb 48mdot figure 10. 48m_usb and 48m_dot phase relationship 66in 66b tpd figure 11. 66in to 66b(0:2) output delay figure
preliminary cy28346-2 document #: 38-07509 rev. *b page 13 of 20 buffer characteristics current mode cpu clock buffer characteristics the current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. the following parameters are used to specify output buffer characteristics: 1. output impedance of the current mode buffer circuit ? ro (see figure 14 ). 2. minimum and maximum required voltage operation range of the circuit ? vop (see figure 14 ). 3. series resistance in the buffer circuit ? ros (see figure 14 ). 4. current accuracy at given configuration into nominal test load for given configuration. 66b pci pcif 1.5- 3.5ns figure 12. buffer mode ? 33v66(0:1); 66buf(0:2) phase relationship pci pcif tpci 3v66 figure 13. unbuffered mode ? 3v66(0:5) to pci (0:6) and pcif(0:2) phase relationship 1.2v 0v iout iout ros ro vdd3 (3.3v +/- 5%) vout = 1.2v max vout slope ~ 1/r 0 figure 14.
preliminary cy28346-2 document #: 38-07509 rev. *b page 14 of 20 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-spec 883e method 1012.1 ? 45 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 15 c/w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ul-94 flammability rating v?0 @1/8 in. ? 10 ppm msl moisture sensitivity level 1 dc parameters (v dd = v dda = 3.3v 5%) parameter description conditions min. typ. max. unit idd3.3v dynamic supply current all frequencies at maximum values [3] 280 ma ipd3.3v power-down supply current pd# asserted note 4 ma cin input pin capacitance 5pf cout output pin capacitance 6pf lpin pin inductance 7nh cxtal crystal pin capacitance measured from the xin or xout pin to ground. 30 36 42 pf ac parameters (v dd = v dda = 3.3v 5%) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max. crystal tdc xin duty cycle 47.5 52.5 47.5 52.5 47.5 52.5 47.5 52.5 % 5, 6, 7 tperiod xin period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 5, 8, 9, 6 vhigh xin high voltage 0.7vdd vdd 0.7vdd vdd 0.7vdd vdd 0.7vdd vdd v vlow xin low voltage 0 0.3vdd 0 0.3vdd 0 0.3vdd 0 0.3vdd v tr/tf xin rise and fall times 10.0 10.0 10.0 10.0 ns 10 tccj xin cycle to cycle jitter 500 500 500 500 ps 8, 11, 6 cpu at 0.7v timing tdc cput and cpuc duty cycle 45 55 45 55 45 55 45 55 % 11, 12, 13 tperiod cput and cpuc period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 11, 12, 13 tskew any cpu to cpu clock skew 100 100 100 100 ps 8, 11, 12 notes: 3. all outputs loaded as per maximum capacitive load table. 4. absolute value = ((programmed cpu iref) x (2)) + 10 ma. 5. this parameter is measured as an average over 1- s duration, with a crystal center frequency of 14.31818 mhz 6. when xin is driven from an external clock source. 7. this is required for the duty cycle on the ref clock out to be as specified. the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within data sheet specifications. 8. all outputs loaded as per table 10 . 9. probes are placed on the pins and measurements are acquired at 1.5v for 3.3v signals (see test and measurement set-up section of this data sheet). 10. measured between 0.2vdd and 0.7vdd. 11. t his measurement is applicable with spread on or spread off. 12. measured at crossing point (vx) or where subtraction of clk- clk# crosses 0 volts measured from vol = 0.175v to voh = 0.525v. 13. test load is rta = 33.2 ohms, rd = 49.9 ohms.
preliminary cy28346-2 document #: 38-07509 rev. *b page 15 of 20 tccj cpu cycle to cycle jitter 150 150 150 150 ps 11, 12, 13 tr/tf cput and cpuc rise and fall times 175 700 175 700 175 700 175 700 ps 11, notes:, 16 rise/fall matching 20% 20% 20% 20% notes:, 15, 13 deltatr rise time variation 125 125 125 125 ps notes:, 13 deltatf fall time variation 125 125 125 125 ps notes:, 13 vcross crossing point voltage at 0.7v swing 280 430 280 430 280 430 280 430 mv 11, 13 cpu at 1.0v timing tdc cput and cpuc duty cycle 45 55 45 55 45 55 45 55 % 11, 12 tperiod cput and cpuc period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 11, 12 tskew any cpu to any cpu clock skew 100 100 100 100 ps 8, 11, 12 tccj cpu cycle to cycle jitter 150 150 150 150 ps 8, 12 differential tr/tf cput and cpuc rise and fall times 175 467 175 467 175 467 175 467 ps 11, 16 se- deltaslew absolute single- ended rise/fall waveform symmetry 325 325 325 325 ps 17, 18 vcross cross point at 1.0v swing 510 760 510 760 510 760 510 760 mv 18 3v66 tdc 3v66 duty cycle4555455545554555%8, 9 tperiod 3v66 period 15.0 15.3 15.0 15.3 15.0 15.3 15.0 15.3 ns 5, 8, 9 thigh 3v66 high time 4.95 4.95 4.95 4.95 ns 19 tlow 3v66 low time 4.55 4.55 4.55 4.55 ns 20 tr / tf 3v66 rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 21 ts k e w unbuffered 3v66 to 3v66 clock skew 500 500 500 500 ps 8, 9 ts k e w buffered 3v66 to 3v66 clock skew 250 250 250 250 ps 8, 9 tccj drcg cycle to cycle jitter 250 250 250 250 ps 8, 9 notes: 14. measured from vol = 0.175v to voh = 0.525v. 15. determined as a fraction of 2*(trise ? tfall)/ (trise + tfall). 16. measurement taken from differential waveform, from ?0.35v to +0.35v. 17. measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86v. rise/fall time matching is defined as ?the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time or minimum clk rise (fall) and maximum clk# fall (rise) time? . this parameter is designed form waveform symmetry. 18. measured in absolute voltage, i.e. single-ended measurement. 19. thigh is measured at 2.4v for non host outputs. 20. tlow is measured at 0.4v for all outputs. 21. probes are placed on the pins, and measurements are acquired be tween 0.4v and 2.4v for 3.3v signals (see test and measuremen t set-up section of this data sheet). ac parameters (v dd = v dda = 3.3v 5%) (continued) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max.
preliminary cy28346-2 document #: 38-07509 rev. *b page 16 of 20 66b tdc 66b(0:2) duty cycle 45 55 45 55 45 55 45 55 % 8, 9 tr / tf 66b(0:2) rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 8, 21 tskew any 66b to any 66b skew 175 175 175 175 ps 8, 9 tpd 66in to 66b(0:2) propagation delay 2.5 4.5 2.5 4.5 2.5 4.5 2.5 4.5 ns 8, 9 tccj 66b(0:2) cycle to cycle jitter 100 100 100 100 ps 8, 9, 22 pci tdc pcif(0:2) pci (0:6) duty cycle 45 55 45 55 45 55 45 55 % 8, 9 tperiod pcif(0:2) pci (0:6) period 30.0 30.0 30.0 30 ns 5, 8, 9 thigh pcif(0:2) pci (0:6) high time 12.0 12.0 12.0 12.0 ns 19 tlow pcif(0:2) pci (0:6) low time 12.0 12.0 12.0 12.0 ns 20 tr/tf pcif(0:2) pci (0:6) rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 21 tskew any pci clock to any pci clock skew 500 500 500 500 ps 8, 9 tccj pcif(0:2) pci (0:6) cycle to cycle jitter 250 250 250 250 ps 8, 9 48m_usb tdc 48m_usb duty cycle 45 55 45 55 45 55 45 55 % 8, 9 tperiod 48m_usb period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 8, 9 tr/tf 48m_usb rise and fall times 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.10 ns 8, 21 tccj 48m_usb cycle to cycle jitter 350 350 350 350 ps 5, 8, 9 48m_dot tdc 48m_dot duty cycle 45 55 45 55 45 55 45 55 % 8, 9 tperiod 48m_dot period 20.837 20.837 20.837 20.837 ns 8, 9 tr/tf 48m_dot rise and fall times 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ns 8, 9 tccj 48m_dot cycle to cycle jitter 350 350 350 350 ps 8, 9 ref tdc ref duty cycle 4555455545554555%8, 9 tperiod ref period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 8, 9 tr / tf ref rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 8, 21 tccj ref cycle to cycle jitter 1000 1000 1000 1000 ps 8, 9 note: 22. this figure is additive to any jitter already present when t he 66in pin is being used as an input. otherwise a 500-ps jitter figure is specified. ac parameters (v dd = v dda = 3.3v 5%) (continued) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max.
preliminary cy28346-2 document #: 38-07509 rev. *b page 17 of 20 test and measurement set-up for differential cpu output signals the following diagram shows lumped test load configurations for the differential host clock outputs. notes: 23. c pu_stp# and pci _stp# setup time with respect to any pcif cloc k to guarantee that the effected clock will stop or start at the next pcif clock?s rising edge. 24. when crystal meets minimum 40-ohm device series resistance specification. tpzl/tpzh output enable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 6 tplz/tpzh output disable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 6 tstable all clock stabili- zation from power-up 333 3ms6 tss stopclock set-up time 10.0 10.0 10.0 10.0 ns 23 tsh stopclock hold time 0 0 0 0 ns 23 tsu oscillator start-up time 1.2 1.2 1.2 1.2 ms 24 ac parameters (v dd = v dda = 3.3v 5%) (continued) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max. measurement point 2pf cput multsel t pcb t pcb cpuc 220? 63.4? 63.4? 475? 33.2? 33.2? measurement point 2pf figure 15. 1.0v test load termination
preliminary cy28346-2 document #: 38-07509 rev. *b page 18 of 20 for single-ended output signals cput multsel t pcb t pcb cpuc 33? 33? measurement point 49.9? 49.9? 2pf measurement point 2pf 221? vdd figure 16. 0.7v test load termination ordering information part number package type product flow cy28346zc-2 56-pin tssop?tube commercial, 0 to 70 c CY28346ZC-2T 56-pin tssop?tape and reel commercial, 0 to 70 c cy28346zi-2 56-pin tssop?tube industrial, 0 to 85 c cy28346zi-2t 56-pin tssop?tape and reel industrial, 0 to 85 c lead-free cy28346zxc-2 56-pin tssop?tube commercial, 0 to 70 c cy28346zxc-2t 56-pin tssop?tape and reel commercial, 0 to 70 c 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc probe output under test load cap - - figure 17.
preliminary cy28346-2 document #: 38-07509 rev. *b page 19 of 20 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawings and dimensions intel is a registered trademark of intel corporation. dial-a-f requency is a registered trademark, and dial-a-db is a trademark, of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. seating plane 1 bsc 0-8 max. gauge plane 28 29 56 1.100[0.043] 0.051[0.002] 0.851[0.033] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] dimensions in mm[inches] min. max. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.42gms part # z5624 standard pkg. zz5624 lead free pkg. 56-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z56 51-85060-*c
preliminary cy28346-2 document #: 38-07509 rev. *b page 20 of 20 document history page document title: cy28346-2 clock synth esizer with differential cpu outputs document number: 38-07509 rev. ecn no. issue date orig. of change description of change ** 122429 12/11/02 rgl new data sheet *a 127147 06/10/03 rgl corrected the value of t su parameter in the ac parameters table from x to 1.2 removed ?preliminary? (it is a final data sheet) *b 333295 see ecn rgl added lead-free for tssop commercial only

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